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Effect of Glitches on the Efficiency of Components' Region-Constrained Placement as a Fast Approach to Reduce FPGA's Dynamic Power Consumption.
Seyed Ebrahim Esmaeili
Nabil I. Khachab
Moustafa Y. Ghannam
Published in:
ISVLSI (2006)
Keyphrases
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power consumption
low power
power reduction
low power consumption
power management
power saving
energy efficiency
save energy
energy management
clock gating
energy saving
single chip
high speed
battery powered
data center
battery life
low cost
real time