Effect of MT and VT CMOS, on Transmission Gate Logic for Low Power 4: 1 MUX in 45 nm Technology.
Meenakshi MishraShyam AkasheShyam BabuPublished in: BIC-TA (2) (2012)
Keyphrases
- nm technology
- low power
- power consumption
- logic circuits
- high speed
- low cost
- wireless transmission
- delay insensitive
- single chip
- power dissipation
- vlsi circuits
- cmos technology
- vlsi architecture
- low power consumption
- digital signal processing
- mixed signal
- image processing
- image sensor
- gate array
- efficient implementation