A Reduced Complexity Instruction Set architecture for low cost embedded processors.
Hanni B. LozanoMabo ItoPublished in: HPCS (2015)
Keyphrases
- reduced complexity
- embedded processors
- single chip
- low cost
- hardware and software
- low power
- instruction set architecture
- vector quantization
- instruction set
- parallel implementation
- embedded systems
- motion estimation algorithm
- real time
- power consumption
- image coder
- multiresolution
- digital camera
- image sensor
- general purpose