On the use of hierarchy in timing verification with statically sensitizable paths.
P. JohannesLuc J. M. ClaesenHugo De ManPublished in: Great Lakes Symposium on VLSI (1992)
Keyphrases
- asynchronous circuits
- model checking
- formal methods
- higher level
- hierarchical structure
- verification method
- information retrieval
- knowledge base
- path finding
- multi agent systems
- low level
- shortest path
- face verification
- handwritten signature verification
- database
- formal verification
- multiscale
- similarity measure
- case study
- neural network
- real time