AES Hardware Implementation Based on FPGA with Improved Throughput.
Andreea Cristina Suiu CristeaAlexandra BalanPublished in: REV (2022)
Keyphrases
- hardware implementation
- field programmable gate array
- signal processing
- software implementation
- efficient implementation
- dedicated hardware
- fpga implementation
- image processing algorithms
- hardware design
- fpga technology
- pipelined architecture
- response time
- pipeline architecture
- parallel architecture
- hardware architecture
- pattern recognition
- fpga device
- xilinx virtex
- memory management
- processing elements
- general purpose processors
- machine learning