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Partial Region and Bitstream Cost Models for Hardware Multitasking on Partially Reconfigurable FPGAs.
Aurelio Morales-Villanueva
Ann Gordon-Ross
Published in:
IPDPS Workshops (2015)
Keyphrases
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bitstream
low cost
field programmable gate array
bit rate
hardware implementation
embedded systems
real time
coding scheme
video quality
reconfigurable hardware
massively parallel
error concealment
error correction
hardware and software
compression algorithm
wavelet coefficients
multiscale
image processing