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A low power 9.5 ENOB 100MS/s pipeline ADC using correlated level shifting.
Kambiz Nanbakhsh
Hamidreza Maghami
Samad Sheikhaei
Nasser Masoumi
Pedram Payandehnia
Published in:
CCECE (2011)
Keyphrases
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low power
power consumption
high speed
low cost
single chip
high power
wireless transmission
vlsi architecture
digital signal processing
low power consumption
vlsi circuits
computer simulation
energy dissipation
real time
delay insensitive