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A 29.12 TOPS/W and 1.13 TOPS/mm2 NAS-Optimized Mixed-Precision DNN Accelerator with Vector Split- and-Combination Systolic in 28nm CMOS.
Kai Li
Hantao Huang
Mingqiang Huang
Chenchen Ding
Longyang Lin
Liebing Ni
Hao Yu
Published in:
CICC (2024)
Keyphrases
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high speed
precision and recall
power consumption
average precision
high resolution
low cost
high precision
low power
combining multiple
circuit design
average error
silicon on insulator