Design of low-power low-area asynchronous iterative multiplier.
Heng YouYong HeiJia YuanWeidi TangXu BaiShushan QiaoPublished in: IEICE Electron. Express (2019)
Keyphrases
- low power
- low power consumption
- single chip
- low cost
- power consumption
- vlsi architecture
- high speed
- logic circuits
- real time
- design process
- power dissipation
- digital signal processing
- gate array
- wireless transmission
- mixed signal
- high power
- power reduction
- efficient implementation
- design considerations
- parallel processing
- ultra low power