Timed state-event automata and alternation for software model checking.
Abdelaziz FellahPublished in: IADIS AC (1) (2009)
Keyphrases
- model checking
- finite state machines
- timed automata
- temporal logic
- finite state
- reachability analysis
- partial order reduction
- formal verification
- transition systems
- formal methods
- symbolic model checking
- formal specification
- verification method
- temporal properties
- model checker
- automated verification
- real time systems
- reactive systems
- software development
- theorem prover
- epistemic logic
- state space
- computation tree logic
- bounded model checking
- process algebra
- software architecture
- regular expressions
- theorem proving
- modal logic
- first order logic
- software systems
- pspace complete
- distributed systems
- deterministic finite automaton
- static analysis
- software engineering