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Low-latency, HDL-synthesizable dynamic clock frequency controller with self-referenced hybrid clocking.

Robert M. SengerEric D. MarsmanGordy A. CarichnerSundus KubbaMichael S. McCorquodaleRichard B. Brown
Published in: ISCAS (2006)
Keyphrases
  • low latency
  • real time
  • highly efficient
  • high speed
  • field programmable gate array
  • information systems
  • massively parallel