An FPGA Accelerator for Bayesian Network Structure Learning with Iterative Use of Processing Elements.
Yasuhiro NittaHideki TakasePublished in: FPT (2020)
Keyphrases
- field programmable gate array
- processing elements
- bayesian network structure learning
- hardware implementation
- hardware architecture
- image processing algorithms
- structure learning
- graph theoretic
- bayesian networks
- reconfigurable hardware
- parallel computing
- embedded systems
- massively parallel
- hardware design
- parallel implementation
- parallel architecture
- parallel computers
- computing systems
- parallel architectures
- signal processing
- low cost
- random access
- hill climbing
- graph theory
- high end
- max min
- fine grained
- associative memory
- artificial neural networks
- pairwise
- functional units
- image processing