Application of Model-Checking Technology to Controller Synthesis.
Alexandre DavidJacob Deleuran GrunnetJan Jakob JessenKim Guldstrand LarsenJacob Illum RasmussenPublished in: FMCO (2010)
Keyphrases
- model checking
- temporal logic
- formal verification
- temporal properties
- verification method
- computation tree logic
- formal specification
- finite state
- bounded model checking
- partial order reduction
- process algebra
- reachability analysis
- automated verification
- controller synthesis
- asynchronous circuits
- transition systems
- deterministic finite automaton
- epistemic logic