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Floorplan-aware application-specific network-on-chip topology synthesis using genetic algorithm technique.
Guoming Lai
Xiaola Lin
Published in:
J. Supercomput. (2012)
Keyphrases
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application specific
network on chip
general purpose
routing algorithm
interconnection networks
network simulator
multi processor
routing protocol
database systems
low cost
multistage
fault tolerant
file system
data transfer