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A Single-Chip Supervised Partial Self-Reconfigurable Architecture for Software Defined Radio.
Oliver Faust
Bernhard H. C. Sputh
Darran Nathan
Sana Rezgui
Andreas Weisensee
Alastair R. Allen
Published in:
IPDPS (2003)
Keyphrases
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single chip
software implementation
low power
cmos image sensor
low cost
highly parallel
control architecture
signal processor
software defined radio
embedded processors
real time
image sensor
high speed
semi supervised
multiscale
machine learning
parallel processing
data acquisition
data collection
data analysis