Proposed low power, high speed adder-based 65-nm Square root circuit.
Chinnaiyan SenthilpariZuraida Irina MohamadS. KavithaPublished in: Microelectron. J. (2011)
Keyphrases
- low power
- square root
- high speed
- cmos technology
- logic circuits
- power dissipation
- nm technology
- power reduction
- kalman filtering
- power consumption
- floating point
- euclidean space
- low voltage
- digital signal processing
- low cost
- arrival rate
- mixed signal
- vlsi circuits
- gate array
- real time
- low power consumption
- image sensor
- probability density function
- data flow
- delay insensitive
- kalman filter
- steady state
- pattern recognition
- computer vision