Design and evaluation of low power and area efficient approximate Booth multipliers for error tolerant applications.
Vishal GundavarapuP. GowthamA. Anita AngelineSasipriya PPublished in: Microprocess. Microsystems (2024)
Keyphrases
- low power
- single chip
- error tolerant
- low cost
- high speed
- power consumption
- vlsi architecture
- low power consumption
- gate array
- logic circuits
- cmos technology
- digital signal processing
- power dissipation
- mixed signal
- vlsi circuits
- design process
- nm technology
- data mining
- ultra low power
- power reduction
- vlsi implementation
- image sensor
- design methodology
- pairwise