Field programmable gate array implementation of a generalized decoder for structured low-density parity check codes.
Lingyan SunB. V. K. Vijaya KumarPublished in: FPT (2004)
Keyphrases
- low density parity check
- ldpc codes
- decoding algorithm
- field programmable gate array
- hardware implementation
- error correction
- fpga technology
- channel coding
- vlsi architecture
- fpga device
- distributed video coding
- message passing
- low complexity
- physical layer
- rate allocation
- low power
- error propagation
- error resilience
- efficient implementation
- xilinx virtex
- source coding
- bit error rate
- error resilient
- real time
- bit plane
- non binary
- belief propagation
- computer simulation
- motion estimation
- pairwise