Compile Time Modeling of Off-Chip Memory Bandwidth for Parallel Loops.

Munara Tolubaeva Yonghong Yan Barbara M. Chapman

Published in: LCPC (2013)

Keyphrases

memory bandwidth
level parallelism
parallel programming
processing power
parallel processing
floating point
high speed
parallel implementation
commodity hardware
memory access
cache misses
cloud computing
processing units
multi core processors
single instruction multiple data