A reconfigurable unit for a clustered programmable-reconfigurable processor.
Richard B. KujothChi-Wei WangDerek B. GottliebJeffrey J. CookNicholas P. CarterPublished in: FPGA (2004)
Keyphrases
- low cost
- functional units
- systolic array
- digital signal
- general purpose
- reconfigurable architecture
- general purpose processors
- single chip
- hardware implementation
- parallel processing
- multi objective evolutionary
- fine grain
- real time
- parallel architecture
- computation intensive
- heterogeneous computing
- dynamic reconfiguration
- interconnection networks
- smart camera
- single processor
- processing elements
- field programmable gate array
- low power
- computer systems
- high speed