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A 0.1-3GHz cell-based fractional-N all digital phase-locked loop using ΔΣ noise-shaped phase detector.
Yao-Chia Liu
Wei-Zen Chen
Mao-Hsuan Chou
Tsung-Hsien Tsai
Yen-Wei Lee
Min-Shueh Yuan
Published in:
CICC (2013)
Keyphrases
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phase locked loop
multipath
high voltage
noise reduction
phase information
noise level
noise model
detection algorithm
signal to noise ratio
neural network
missing data
high frequency
noisy data
gaussian noise
microscopy images