ROMA: A Reconfigurable On-chip Memory Architecture for Multi-core Accelerators.
Shantian QinWenming LiZhihua FanZhen WangTianyu LiuHaibin WuKunming ZhangXuejun AnXiaochun YeDongrui FanPublished in: HPCC/DSS/SmartCity/DependSys (2023)
Keyphrases
- low cost
- level parallelism
- field programmable gate array
- memory access
- digital signal processors
- single chip
- reconfigurable hardware
- multithreading
- memory subsystem
- hardware implementation
- analog vlsi
- memory management
- systolic array
- host computer
- functional units
- high speed
- vlsi implementation
- associative memory
- processing elements
- memory bandwidth
- main memory
- cmos image sensor
- multi core processors
- random access memory
- nm technology
- real time
- cmos technology
- evolvable hardware
- computing platform
- general purpose
- power consumption
- computing systems
- embedded systems