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High-Level Design of an Asynchronous Packet-Routing Chip.
Mark B. Josephs
Rudolf H. Mak
Jan Tijmen Udding
Tom Verhoeff
Jelio Todorov Yantchev
Published in:
Designing Correct Circuits (1992)
Keyphrases
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high level
user interface
low level
circuit design
response time
shortest path
single chip
low cost
high speed
design process
network topology
routing problem
evolvable hardware
modular design
high level synthesis