A Hardware Optimized High Throughput LDPC Decoder Supporting 3 Tb/s in 28 nm CMOS.
Lukasz LopacinskiAlireza HasaniGoran PanicNebojsa MaleticJesús GutiérrezMilos KrsticEckhard GrassRolf KraemerPublished in: PIMRC (2022)
Keyphrases
- high throughput
- silicon on insulator
- low cost
- ldpc codes
- low density parity check
- low latency
- data acquisition
- microarray
- distributed source coding
- circuit design
- biological data
- genome wide
- distributed video coding
- systems biology
- turbo codes
- decoding algorithm
- low complexity
- cmos technology
- genomic data
- error correction
- high speed
- protein protein interactions
- mass spectrometry data
- real time
- proteomic data
- metal oxide semiconductor
- compressive sensing
- image sensor
- gene expression
- low power
- mass spectrometry
- message passing
- dna sequencing
- motion estimation
- microarray data
- power consumption
- analysis of gene expression