Design and analysis of a hybrid encoded low power multiplier with reduced transition activity technique.

S. Saravanan M. Madheswaran

Published in: ICWET (2010)

Keyphrases

low power
high speed
low cost
power consumption
single chip
low power consumption
vlsi architecture
gate array
power dissipation
logic circuits
design process
digital signal processing
cmos technology
vlsi circuits
image quality
power reduction
wireless transmission
signal processing