Design of 50 MHz PLL using indigenous SCL 180 nm CMOS Technology.

Chandra Shekhar Shafi Qureshi

Published in: iSES (2021)

Keyphrases

cmos technology
low power
spl times
parallel processing
power consumption
power dissipation
low voltage
high speed
mixed signal
computer vision
low cost
nm technology
image processing
case study
silicon on insulator
single chip