Login / Signup
System level interconnect design for network-on-chip using interconnect IPs.
Jian Liu
Meigen Shen
Li-Rong Zheng
Hannu Tenhunen
Published in:
SLIP (2003)
Keyphrases
</>
power dissipation
network on chip
design process
high speed
power consumption
low power
quality of service
ad hoc networks
design methodology
digital signal processing