A 100 MHz, 0.8-to-1.1 V, 170 mA Digital LDO With 8-Cycles Mean Settling Time and 9-Bit Regulating Resolution in 180-nm CMOS.
Zheyi YuanShiquan FanChenxi YuanLi GengPublished in: IEEE Trans. Circuits Syst. II Express Briefs (2020)
Keyphrases
- nm technology
- cmos technology
- mixed signal
- low power
- power consumption
- analog to digital converter
- high speed
- metal oxide semiconductor
- circuit design
- low cost
- low voltage
- image sensor
- power dissipation
- cmos image sensor
- flip flops
- vlsi circuits
- parallel processing
- random access memory
- silicon on insulator
- real time
- low resolution
- high resolution
- digital media
- digital libraries
- solid state
- clock gating
- analog vlsi
- digital signal processing
- digital curves
- neural network