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Novel Dual Work Function Buried Channel Array Transistor Process Design for Sub-17 nm DRAM.
Dong-Sik Park
Dong-Hyun Im
Yun-Jung Kim
Sung Sam Lee
Byung-Jae Kang
Jae-Hong Seo
Taewoong Koo
Byoungdeog Choi
Published in:
IEEE Access (2024)
Keyphrases
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design process
user interface
case study
high speed
metamodel
multi channel
circuit design