A parallel DSP-based neural network emulator with CMOS VLSI packet switching hardware.
Markus SchwarzBedrich J. HostickaM. KesperPeter RichertMichael SchollesPublished in: ASAP (1994)
Keyphrases
- neural network
- high speed
- single chip
- digital signal processing
- signal processing
- digital signal processor
- low cost
- packet switching
- low power
- power dissipation
- chip design
- vlsi circuits
- massively parallel
- circuit design
- real time
- vlsi implementation
- hardware implementation
- power consumption
- neural network model
- parallel processing
- quality of service
- image sensor
- focal plane