Flexible hardware-friendly digital architecture for 2-D separable convolution-based scaling.
Francisco Cardells-TormoJordi Arnabat-BenedictoPublished in: IEEE Trans. Circuits Syst. II Express Briefs (2006)
Keyphrases
- hardware architecture
- real time
- low cost
- hardware and software
- image processing
- vlsi implementation
- software implementation
- hardware design
- hardware software
- hardware implementation
- circuit design
- dedicated hardware
- pipeline architecture
- memory management
- dynamic reconfiguration
- hardware architectures
- vlsi architecture
- neural network
- multi core processors
- embedded systems
- mixed signal
- xilinx virtex
- software architecture
- camera phones
- content addressable
- lightweight
- central processor
- digital signal processors