A 400-Gb/s and Low-Power Physical-Layer Architecture for Next-Generation Ethernet.

Masashi Kono Akihiro Kambe Hidehiro Toyoda

Published in: ICC (2011)

Keyphrases

low power
high speed
physical layer
vlsi architecture
power consumption
cmos technology
low cost
real time
communication protocol
data acquisition
low density parity check
wireless communication
application layer
network layer
tcp ip
resource utilization
smart grid
frame rate