A delay spread based low power reconfigurable FFT processor architecture for wireless receiver.
Mohd. HasanTughrul ArslanJohn S. ThompsonPublished in: SoC (2003)
Keyphrases
- low power
- low cost
- single chip
- high speed
- vlsi architecture
- wireless transmission
- power consumption
- ultra low power
- power reduction
- gate array
- power dissipation
- cmos technology
- systolic array
- real time
- nm technology
- mixed signal
- digital signal processing
- hardware implementation
- vlsi circuits
- signal processor
- parallel architecture
- wireless networks
- logic circuits
- hardware and software
- wireless communication
- frequency domain
- multi core processors
- low power consumption
- functional units
- data flow
- general purpose
- image sensor
- multi hop
- floating point
- mobile devices