An FPGA-based hardware accelerator for simulating spatiotemporal neurons.
Ghaith TarawnehJenny ReadPublished in: ICECS (2014)
Keyphrases
- field programmable gate array
- hardware implementation
- hardware architecture
- embedded systems
- hardware design
- parallel computing
- computing systems
- image processing algorithms
- processing elements
- low cost
- space time
- spatial and temporal
- high end
- massively parallel
- hardware software
- neural network
- hardware architectures
- receptive fields
- associative memory
- parallel implementation
- neural model
- data mining
- real time
- learning rules
- signal processing
- video sequences