Performance and Power Modeling of On-Chip Bus System for a Complex SoC.

Hyun Lee Je-Hoon Lee Kyoung-Rok Cho

Published in: IEICE Trans. Electron. (2010)

Keyphrases

high speed
low power
low cost
power consumption
real time
real world
modeling method
dynamic bayesian networks
ibm power processor
power management
modeling language
complex systems
complex data
high level
learning algorithm
neural network
chip design
data sets