Automatic Generation of Optimized and Synthesizable Hardware Implementation from High-Level Dataflow Programs.
Khaled JerbiMickaël RauletOlivier DéforgesMohamed AbidPublished in: VLSI Design (2012)
Keyphrases
- hardware implementation
- field programmable gate array
- high level
- low level
- intermediate level
- parallel computing
- signal processing
- efficient implementation
- control flow
- hardware architecture
- hardware design
- fpga implementation
- software implementation
- high level programming
- dedicated hardware
- image processing algorithms
- programming language
- data flow
- automatically generate
- embedded systems
- pipeline architecture
- higher level
- machine learning
- general purpose processors
- hardware description language
- parallel architecture
- computer vision
- query processing
- image binarization
- shift register
- open source
- design methodology