Correctly rounded floating-point division for DSP-enabled FPGAs.
Bogdan PascaPublished in: FPL (2012)
Keyphrases
- floating point
- digital signal processing
- square root
- field programmable gate array
- signal processing
- digital signal processor
- fixed point
- instruction set
- interval arithmetic
- bayesian networks
- sparse matrices
- floating point arithmetic
- image processing
- parallel computing
- hardware implementation
- efficient implementation
- operating system
- general purpose
- dynamic programming