Simultaneous reconfiguration of issue-width and instruction cache for a VLIW processor.
Fakhar AnjamStephan WongLuigi CarroGabriel L. NazarMateus B. RutzigPublished in: ICSAMOS (2012)
Keyphrases
- level parallelism
- memory hierarchy
- cache misses
- instruction set
- memory bandwidth
- memory subsystem
- main memory
- memory access
- prefetching
- computing power
- computer architecture
- multithreading
- processor core
- shared memory multiprocessors
- multiprocessor systems
- secondary storage
- embedded processors
- memory management
- manufacturing systems
- embedded systems
- speculative execution
- data structure
- multi core processors
- floating point
- access patterns
- instructional design
- data access
- high speed
- query processing