A novel low-cost high-performance VLSI architecture for MPEG-4 AVC/H.264 CAVLC decoding.
Hsiu-Cheng ChangChien-Chang LinJiun-In GuoPublished in: ISCAS (6) (2005)
Keyphrases
- vlsi architecture
- low cost
- mpeg avc
- low power
- real time
- high definition
- video coding standard
- video codec
- video coding
- vlsi implementation
- bit rate
- coding efficiency
- low complexity
- mode decision
- power consumption
- motion compensation
- scalable video coding
- coding method
- video compression
- high speed
- highly efficient
- macroblock
- motion vectors
- motion estimation
- motion compensated
- inter frame
- bitstream
- rate distortion