Design Validation of Recurrent Signal Processor FPGA prototype.

Yury Stepchenkov Dmitry Khilko Yury Shikunov Georgy Orlov

Published in: EWDTS (2021)

Keyphrases

single chip
high speed
signal processing
neural network
design process
hardware design
signal processor
real time
multimedia
verilog hdl
high resolution
low cost
efficient implementation
low power