A high performance hardware architecture for the H.264/AVC half-pixel motion estimation refinement.
Marcel Moscarelli CorrêaMateus Thurow SchoenknechtLuciano Volcan AgostiniPublished in: SBCCI (2010)
Keyphrases
- hardware architecture
- motion estimation
- inter frame
- video coding
- search range
- intra frame
- variable block size
- coding efficiency
- motion estimator
- video compression standard
- rate distortion
- low complexity
- motion vectors
- macroblock
- motion compensation
- video codec
- hardware implementation
- block matching motion estimation
- computational complexity
- video encoder
- bit rate
- video compression
- image sequences
- video sequences
- motion compensated
- reference frame
- hardware architectures
- optical flow
- block matching
- video coding standard
- super resolution
- associative memory
- computer vision
- field programmable gate array
- motion field
- prediction error
- intra prediction
- bitstream
- pixel wise
- parallel computers
- feature extraction