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Securing Hardware Accelerators: A New Challenge for High-Level Synthesis.

Christian PilatoSiddharth GargKaijie WuRamesh KarriFrancesco Regazzoni
Published in: IEEE Embed. Syst. Lett. (2018)
Keyphrases
  • high level synthesis
  • parallel architecture
  • bayesian networks
  • artificial intelligence
  • image segmentation
  • signal processing
  • level set
  • design space exploration