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Securing Hardware Accelerators: A New Challenge for High-Level Synthesis.
Christian Pilato
Siddharth Garg
Kaijie Wu
Ramesh Karri
Francesco Regazzoni
Published in:
IEEE Embed. Syst. Lett. (2018)
Keyphrases
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high level synthesis
parallel architecture
bayesian networks
artificial intelligence
image segmentation
signal processing
level set
design space exploration