A 133.6TOPS/W Compute-In-Memory SRAM Macro with Fully Parallel One-Step Multi-Bit Computation.
Edward Jongyoon ChoiInjun ChoiChanhee JeonGichan YunDonghyeon YiSohmyung HaIk-Joon ChangMinkyu JePublished in: CICC (2022)
Keyphrases
- random access memory
- parallel computation
- multi step
- efficient computation
- design considerations
- parallel computers
- parallel hardware
- memory requirements
- parallel processing
- parallel computing
- low voltage
- multi threaded
- matrix inversion
- virtual memory
- database systems
- shared memory
- power consumption
- bit parallel
- level parallelism
- memory space
- parallel implementation
- main memory
- parallel algorithm
- multi core processors
- memory management
- efficiently computing
- massively parallel
- wireless sensor networks