120-core microAptiv MIPS Overlay for the Terasic DE5-NET FPGA board.

Chethan Kumar H. B Prashant Ravi Gourav Modi Nachiket Kapre

Published in: FPGA (2017)

Keyphrases

high speed
real time image processing
hardware implementation
low cost
real time
overlay network
hardware design
hardware architecture
genetic algorithm
website
object oriented
field programmable gate array
dedicated hardware