Hierarchical representation of on-chip context to reduce reconfiguration time and implementation area for coarse-grained reconfigurable architecture.
Yansheng WangLeibo LiuShouyi YinMin ZhuPeng CaoJun YangShaojun WeiPublished in: Sci. China Inf. Sci. (2013)
Keyphrases
- coarse grained
- hierarchical representation
- fine grained
- reconfigurable architecture
- object centered
- coarse to fine
- multithreading
- systolic array
- multiresolution
- high level
- machine learning
- multiscale
- contact maps
- signal processing
- higher order
- parallel processing
- message passing
- shared memory
- word sense
- image analysis
- knowledge base