Login / Signup

A Parallel Simulated Annealing Approach for Floorplanning in VLSI.

Jyh-Perng FangYang-Lang ChangChih-Chia ChenWen-Yew LiangTung-Ju HsiehMuhammad T. SatriaChin-Chuan Han
Published in: ICA3PP (2009)
Keyphrases