Dataflow-Functional High-Level Synthesis for Coarse-Grained Reconfigurable Accelerators.
Claudio RubattuFrancesca PalumboCarlo SauRubén SalvadorJocelyn SérotKarol DesnosLuigi RaffoMaxime PelcatPublished in: IEEE Embed. Syst. Lett. (2019)
Keyphrases
- coarse grained
- high level synthesis
- fine grained
- parallel architecture
- parallel computing
- shared memory
- field programmable gate array
- dynamic reconfiguration
- protein sequences
- functional units
- hardware implementation
- computing systems
- data flow
- parallel algorithm
- distributed systems
- high level
- knowledge base
- message passing
- pairwise
- image processing