A pipelined architecture for user-defined floating-point complex division on FPGA.
Shaobing HuangLi YuFang-Jian HanYiwen LuoPublished in: CCECE (2017)
Keyphrases
- user defined
- floating point
- pipelined architecture
- field programmable gate array
- hardware implementation
- data types
- fixed point
- low cost
- instruction set
- sparse matrices
- query language
- data analysis
- management system
- floating point arithmetic
- real time
- embedded systems
- data management
- distributed systems
- relational databases
- computer vision
- databases