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A high-level synthesis flow for the implementation of iterative stencil loop algorithms on FPGA devices.
Alessandro Antonio Nacci
Vincenzo Rana
Francesco Bruschi
Donatella Sciuto
Ivan Beretta
David Atienza
Published in:
DAC (2013)
Keyphrases
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high level synthesis
hardware architectures
software implementation
learning algorithm
artificial intelligence
pattern recognition
low cost
efficient implementation
image processing algorithms
np hard
intelligent agents
hardware implementation
dedicated hardware
parallel hardware