A Low-Power Multiplier With the Spurious Power Suppression Technique.
Kuan-Hung ChenYuan-Sun ChuPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2007)
Keyphrases
- low power
- power consumption
- high power
- high speed
- low cost
- power management
- single chip
- power reduction
- power dissipation
- low power consumption
- digital signal processing
- power saving
- energy dissipation
- wireless transmission
- vlsi circuits
- logic circuits
- energy saving
- cmos technology
- energy efficiency
- vlsi architecture
- delay insensitive
- image processing
- image sensor